Control hazards in computer architecture

Further information: Types [ ] Data hazards [ ] Data hazards occur when instructions that exhibit • read after write (RAW), a true dependency • write after read (WAR), an anti-dependency • write after write (WAW), an output dependency Read after read (RAR) is not a hazard case. Consider two instructions i1 and i2, with i1 occurring before i2 in program order. Read after write (RAW) [ ] ( i2 tries to read a source before i1 writes to it) A read after write (RAW) data hazard refers to a situation where an instruction refers to a result that has not yet been calculated or retrieved. This can occur because even though an instruction is executed after a prior instruction, the prior instruction has been processed only partly through the pipeline. Example [ ] For example: i1. R2<- R5 + R3 i2. R4 <- R2 + R3 The first instruction is calculating a value to be saved in register R2, and the second is going to use this value to compute a result for register R4. However, in a A data dependency occurs with instruction i2, as it is dependent on the completion of instruction i1. Write after read (WAR) [ ] ( i2 tries to write a destination before it is read by i1) A write after read (WAR) data hazard represents a problem with concurrent execution. Example [ ] For example: i1. R4 <- R1 + R5 i2. R5<- R1 + R2 In any situation with a chance that i2 may finish before i1 (i.e., with concurrent execution), it must be ensured that the result of register R5 is not stored before i1 has had a chance t...

Data Hazards occur when an instruction depends on the result of previous instruction and that result of instruction has not yet been computed. whenever two different instructions use the same storage. the location must appear as if it is executed in sequential order. There are four types of data dependencies: Read after Write (RAW), Write after Read (WAR), Write after Write (WAW), and Read after Read (RAR). These are explained as follows below. • Read after Write (RAW) : It is also known as True dependency or Flow dependency. It occurs when the value produced by an instruction is required by a subsequent instruction. For example, ADD R1, --, --; SUB --, R1, --; Stalls are required to handle these hazards. • Write after Read (WAR) : It is also known as anti dependency. These hazards occur when the output register of an instruction is used right after read by a previous instruction. For example, ADD --, R1, --; SUB R1, --, --; • Write after Write (WAW) : It is also known as output dependency. These hazards occur when the output register of an instruction is used for write after written by previous instruction. For example, ADD R1, --, --; SUB R1, --, --; • Read after Read (RAR) : It occurs when the instruction both read from the same register. For example, ADD --, R1, --; SUB --, R1, --; Since reading a register value does not change the register value, these Read after Read (RAR) hazards don’t cause a problem for the processor. Handling Data Hazards : These are various meth...